Handout Question A. What is the default value of the ADC prescaler?
CLK_PER divided by 128
Handout Question B.1. What is the prescaler that fixes the value of CLK_PER?
=> Division by 2
Handout Question B.2. What is the default value of the PEN bit of the MCLKCTRLB register?
=> 0
Handout Question B.3. What do you conclude from the value of the PEN bit value?
=> That no prescaler is used, meaning that CLK_MAIN will be the clock signal directly from the 16/20 MHz clock.
Handout Question C. What is the minimum allowable ADC prescaler that must be used for the CLK_PER signal corresponding to the 16 MHz signal of the oscillator, keeping in mind the allowed prescaler values in the CTRLC register?
=> CLK_PER divided by 16
Handout Question D. With the appropriately modified ADC_SingleConvClass.ino file, enter the various values of the ADC output value from your code for all of the possible ADC prescaler values:
=>
Value for CLK_PER divided by 2:
1023
Value for CLK_PER divided by 4:
1023
Value for CLK_PER divided by 8:
632, 672, 701, 719, 728, 736, 742, 743, 748, 747
Value for CLK_PER divided by 16:
673, 697, 717, 728, 738, 742, 747, 745, 750, 748
Value for CLK_PER divided by 32:
673, 699, 717, 726, 736, 740, 742, 746, 747, 750
Value for CLK_PER divided by 64:
698, 713, 726, 735, 738, 743, 748, 746, 751, 749
Value for CLK_PER divided by 128:
627, 676, 698, 717, 727, 733, 741, 742, 745, 746, 749
Value for CLK_PER divided by 256:
670, 694, 713, 726, 733, 739, 742, 746, 745, 747, 749, 748, 750